The present invention relates to programming flash memories and, more particularly, to a method of programming a flash memory such as a NAND flash memory with reduced program disturb.
Flash memory devices are used in various applications to store digital information. A basic flash cell consists of a transistor with a floating gate positioned between the channel and the transistor's control gate. The threshold voltage of the transistor is defined as the lowest voltage that, when applied to the control gate of the transistor, changes the channel state from a non-conducting state to a conducting state. This voltage is affected by the amount of negative charge trapped in the floating gate: the more charge, the higher the threshold voltage of the cell. SLC (Single Level Cell)-type devices use cells with zero charged floating gates to represent a “1” state and cells with negatively charged floating gates to represent a “0” state. The cell state can be represented by the cell's threshold voltage, in this case using two voltage levels, “1” state voltage and “0” state voltage. Although cells may have slightly different “0” state voltages, applying a voltage that is between the “1” state voltage and the “0” state voltage to the control gate causes the “1” state cells to conduct, but the “0” state cells stay in the non-conducting state.
The most common kind of Multi Level Cell (MLC)-type devices uses 4 charge amounts in the floating gate, including zero charge, so the cell state can be represented by 4 voltage levels, thus a MLC cell stores 2 bits per cell. Generally, N bits per cell can be represented using 2N voltage levels. Using high number of bits per cell allows producing Flash devices with high data density and thus reduces the overall cost per Flash device.
A NAND Flash device consists of arrays of cells, called blocks. A block is built as a matrix in which the rows are word lines (WL) that connect the control gates of the cells, and each column is a chain of floating gate cells that are connected to a corresponding bit line (BL) on one side of the chain via a first select gate SGD, and on the other side of the chain to a common source line via a second select gate SGS. The SGD gates are connected to form a SGD line and the SGS gates are connected to form a SGS line, similar to the manner in which the control gates are connected to from the WL. An example of one block of a NAND Flash array with 8 WL's and 4256 BL's is shown in FIG. 1. Examples of such arrays are given in the following U.S. patents that are incorporated by reference for all purposes as if fully set forth herein: U.S. Pat. No. 5,774,397; U.S. Pat. No. 6,046,935. A physical page of such a memory includes the cells that have their transistor gates connected to the same WL. Each page in the example shown in FIG. 1 includes 4256 cells, so the block shown in FIG. 1 includes 8 pages of 4256 cells each, for a total of 34,048 cells. During an erase operation of a NAND block the whole block is erased as described below, and program and read operations on NAND cells are done on a per-page basis. Consequently, for the purpose of the present invention a block of cells is defined as the smallest chunk of cells that are erased simultaneously, and a page of cells is defined as the smallest chunk of cells that are written (programmed) simultaneously. (For historical reasons, writing to a flash cell is called “programming” the cell. “Writing” and “programming” are used interchangeably herein.)
An erase operation involves applying a high voltage between the C-p-well (an area in the silicon structure of the Flash device that is located under the cells and that is common to all the cells) and all the WL's of the selected block, with the WL's being held at 0 voltage. This high voltage causes the affected floating gates to discharge any charge that was trapped in the floating gate by a previous programming operation, thus bringing the cells to the erased state.
A programming operation involves applying a high voltage to the selected WL and applying a lower voltage to other WL's so as to bring the other WL's to a conducting state. The BL's of the cells that are to be programmed are kept at 0 voltage so the cells are put under stress caused by the high voltage of the selected WL and 0 voltage of the BL's. The BL's of the cells that are not intended to be programmed are connected to a voltage level such that the stress caused by the difference between the BL's and the voltage applied to the WL is not enough to cause a change in the floating gate charges of the cells. The programming process is made up of a series of programming pulses, interleaved with verification operations in which each cell's target threshold voltage is applied to the cell gate to check if more charge should be trapped in the floating gate. If more charge needs to be trapped in any cell's floating gate, another programming pulse is applied with a slightly higher amplitude or longer duration than the preceding programming pulse. If the cell has reached its target threshold voltage, its further programming is inhibited by applying an appropriate voltage level to its BL, similar to the cells that are not intended to be programmed.
A read or verify process involves applying one or more reference voltage levels to a cell gate and checking whether the cell is conductive. This reference voltage is applied to the selected WL. The other WL's are connected to a read pass voltage that makes the other cells conductive, and the cell's chain's SGS line is held at conducting state to connect the chain to the C-source line, which is kept at 0 voltage. The BL is precharged with some voltage, and if the reference voltage applied to the selected WL is higher than the tested cell's threshold voltage, then the tested cell becomes conducting, which makes the whole chain conducting, and the precharged BL voltage decreases. If the reference voltage applied to the tested cell is lower than the tested cell's threshold voltage, then the tested cell prevents conducting through the chain of cells and the voltage applied to the BL stays at its precharged level. Sense amplifiers connected to the BL's make the decision about the cell's state. A reference voltage that is used to verify the correct programming of one or more memory cells is termed a “verify voltage” herein.
The read operation of a SLC device uses one reference voltage level that is between the “0” and “1” voltage levels. The read operation in a MLC device with 4 cell states uses 3 reference voltage levels, and a device that stores N bits per cell, that are represented by 2N states, needs 2N−1 reference voltage levels for read operations.
Phenomena related to the Flash programming operation, such as cross coupling and program disturb, cause the actual threshold voltage distributions of a population of flash cells to take the form of 2N voltage groups for an N-bits-per-cell device. An example of threshold voltage distributions in a device with 8 nominal threshold voltage levels is shown in FIG. 2. Ideally, the corresponding reference voltages for reading the cells of such a device should be between the voltage groups: VR1, VR2, VR3, VR4, VR5, VR6 and VR7 as shown in FIG. 2.
The threshold voltage level groups should be separated for reliable read operation, and using a high number of voltage levels implies a larger difference between the lowest voltage level and the highest voltage level. High voltage levels require using a high programming pulse voltage applied to the WL during the programming operation, and this increases a program disturb effect as shown below.
A program operation puts a stress on the cells to be programmed, by applying a high voltage to the selected WL and 0 voltage to the selected BL, with the unselected WL's kept at conducting voltage and unselected BL's kept at some voltage that is lower than the programming voltage. Although all the gates of the selected page are connected to the high voltage applied to the selected WL, the programming stress is applied only to the cells at the intersections of the selected WL and the selected BL's, as the difference between the WL voltage and unselected BL's is lower than the difference between the WL voltage and the selected BL's. In an ideal device only the selected cells would change their floating gate charge during the programming operation, but in a real device the smaller stress between the selected WL and unselected BL's cause a small change in the charges on these floating gates too. This is known as the program disturb phenomenon and its effect is mainly seen in the low voltage level cells and is increased when using higher programming voltages. An example of a cell threshold voltage distribution after a programming operation that includes a program disturb effect is shown in FIG. 6 and is described below.
The following example illustrates the program disturb effect in a simplified situation in which the data to be programmed to a flash memory are to be represented by 8 voltage levels, #0 through #7. Different programming techniques exist, but they usually use a sequential increase of the programming voltage to program the different voltage levels, so this example assumes programming level #1, then #2, and so on till #7. This example also assumes that the cells to be programmed to the level #N are first programmed to levels # 1 through #(N−1) and then using higher programming voltages these cells are programmed to level #N. The example assumes that the user data are represented by all 8 voltage levels and the user data are evenly distributed among these 8 levels.
The programming starts with all cells in the erased state, as shown in FIG. 3. The voltage distribution after programming the level #1 is shown in FIG. 4, where the level #1 includes the cells that are to be programmed to level #1 and also the cells that are to be programmed to levels #2 through #7. The BL's of the cells that are to be programmed to level #1 are put in an inhibit state after these cells reach their target charge in their floating gates. FIG. 5 shows the voltage distribution after programming to level #2, where the level #2 includes the cells that are to be programmed to level #2 and also the cells that are to be programmed to levels #3 through #7. The voltage distribution after programming level #7 is shown in FIG. 6, where the widening and shifting of the low level distributions, such as distributions #0 and #1, is caused mainly by the program disturb phenomenon when programming high levels such as levels #6 and #7. It can be seen that some of the level #1 cells have become level #2 cells, so when the data are read from the flash they will be read with errors. Various techniques try to adjust the voltage levels being programmed so the final voltage distribution is narrow and in the right place, but the fact that the program disturb effect depends on the data content that is programmed makes it difficult to design a proper technique that works for all data patterns. For example the location of the level #1 could be set to a lower voltage first, so the program disturb caused by the programming the levels #6 and #7 would bring the #1 distribution to the right position, but this technique would fail for a page that does not include data represented by levels #6 and #7, as in this case the program disturb effect caused by the lower levels is much smaller, and some of the #1 cells would be read as #0 cells.
There is thus a widely recognized need for, and it would be highly advantageous to have, a method of programming flash cells that overcomes the disadvantages of presently known methods as described above.